1. Field of the Invention
The invention relates to a circuit arrangement and a process for regeneration and synchronization of a high-bit rate digital signal, which can have any desired phase position and be subject to jitter and wander from the system clock.
2. Description of the Prior Art
In conventional synchronization equipment and processes, phase-locked loops (PLL) are used, by means of which the sampling of a digital signal is carried out. However, PLLs contain relatively large capacitances which are poorly integrated. In addition, undesired coupling of several PLLs frequently cause problems, such as, for example, beating and hunting.
A circuit arrangement for the regeneration and synchronization of a high-bit-rat digital signal is also known from German Patent 35 43 392, which features a delay line, a multiplexer, and an evaluation circuit. The evaluation is carried out, among other things, by the use of flip-flops and another delay line. In this process, the digital signal is sampled in the region of its edge, with a window function being provided. It has been found, however, that in an evaluation of a signal of this type, jitter can lead to incorrect information, and also the control region of the circuit arrangement is restricted.